Design Verification Engineers / Lead for PCIe Design IP R&D Team at Bangalore
Experience: 4 – 15 Years
Location: Bangalore / Noida
Notice Period: Immediate to 60 Days or serving notice period
Job Description:
We are looking for experienced Design Verification (DV) Engineers and Leads with strong SV / UVM/ Testbench development skills with working knowledge of PCIe /CXL protocol.
Key Responsibilities:
- Lead end-to-end IP verification activities
- Develop detailed test plans and verification strategies
- Build and maintain UVM-based testbenches using System Verilog
- Knowledge of protocols (AXI/AHB/APB ) PCIe is a must.